module PC(
    input wire clk,
    input wire rst,
    input wire [31:0] jump_pc,
    input wire jump,
    input wire stall,

    output reg [31:0] pc,
    output reg [31:0] pc4

    );

    reg flag=0;
    always @ (posedge clk or posedge rst) begin
        if(rst) begin pc <= 0;
           
            flag <=0;
        end
        else if(flag==0 && pc ==0)begin
          pc<=0;
         
          flag<=1;
        end
        else if(jump)begin
          pc <= jump_pc;
        end
        else if(stall)begin
          pc <= pc;
        end
        else begin
          pc<=pc4;

        end
    end

    always @(*) begin
      pc4 = pc + 32'h4;
    end
endmodule
